1. Field of the Invention
The present invention relates to a semiconductor device and more particularly, to a semiconductor device with the trench isolation structure and a fabrication method thereof.
2. Description of the Prior Art
The isolation structure is essential for Integrated Circuits (ICs) to electrically isolate electronic elements or devices on a semiconductor substrate. To implement the isolation structure, conventionally, two isolation techniques have been used.
In a first one of the isolation techniques, the isolation dielectric is formed on a main surface of the semiconductor substrate by the well-known LOcal Oxidation of Silicon (LOCOS) method. The isolation dielectric is typically made of a thick silicon dioxide (SiO.sub.2) layer having a pattern of a wanted isolation region.
In a second one of the isolation techniques, the isolation dielectric is formed to fill a trench formed in a surface region of the semiconductor substrate. The trench has a pattern of a wanted isolation region and is filled with the isolation dielectric, thereby constituting the trench isolation structure. The isolation dielectric is typically made of SiO.sub.2.
A conventional semiconductor device including the trench isolation structure is shown in FIG. 1.
In FIG. 1, an isolation trench 102 is formed in a surface region of a single-crystal silicon substrate 101. The trench 102 is filled with an isolation dielectric 103. As the isolation dielectric 103, SiO.sub.2 is usually used.
A diffusion region 111, which is opposite in conductivity type to the substrate 101, is formed in the surface region of the substrate 101. The end of the diffusion region 111 is contacted with the opposing edge of the isolation dielectric 103.
An interlayer insulating layer 110 is formed on the surface region of the substrate 101 to cover the diffusion region 111 and the isolation dielectric 103. The interlayer insulating layer 110 has a contact hole 114' uncovering the diffusion region 111.
A metallic wiring layer 109 is formed on the interlayer insulating layer 110 to overlap with the diffusion region 111 and the isolation trench 102. The wiring layer 109 is contacted with and electrically connected to the underlying diffusion region 111 through the contact hole 114' of the interlayer insulating layer 110.
The position of the contact hole 114' is designed so that the contact hole 114' uncovers the diffusion region 111 alone, in other words, the contact hole 114' is not contacted with the isolation dielectric 103. The designed, correct position of the contact hole 114' is indicated by a reference numeral 114 in FIG. 1.
When the position of the contact hole 114' deviates from its correct position 114 due to the positional and/or dimensional fluctuation in the fabrication process sequence, the wiring layer 109 on the interlayer insulating layer 110 tends to be contacted with the substrate 101 at a contact area 112 through the contact hole 114' of the interlayer insulating layer 110 and an opening 115 of the isolation dielectric 103, as shown in FIG. 1. This is caused by the fact that the isolation trench 102 and therefore the isolation dielectric 103 has vertical walls, which is unlike the isolation structure using the LOCOS method.
Thus, there is a problem that a leakage current flows between the wiring layer 109 and the substrate 101 due to the positional error of the contact hole 114'.
FIG. 2 shows another cause of the leakage current between the wiring layer 109 and the substrate 101. For simplification of description, the same reference numerals as those in FIG. 1 are attached to the same elements in FIG. 2, and the interlayer dielectric layer 110 and the metallic wiring layer 109 are omitted.
In FIG. 2, the isolation dielectric 103 filling the isolation trench 102 is made of a material with a large stress such as silicon nitride (Si.sub.3 N.sub.4). Crystal defect regions 113 tend to be generated at the interface of the isolation dielectric 103 with the substrate 101 and the diffusion region 111 after heat treatment. The crystal defect regions 113 will cause the above-described leakage current problem between the diffusion region 111 and the substrate 101.
The other, relating conventional trench isolation structures are disclosed in the Japanese Non-Examined Patent Publication Nos. 4-27141 published in 1992 and 5-299497 published in 1993.